Rust India Conference 2026

Session Description

Writing software for bare-metal systems traditionally relies on C/C++, trusting the programmer to manually manage memory, hardware state, and concurrency. Rust provides the tools to enforce these constraints at compile time, but applying Rust to undocumented, bare silicon requires a deep understanding of both the compiler’s behavior and the processor’s physical architecture.

This talk dissects the engineering of a custom bare-metal operating system for the Raspberry Pi 5. The Pi 5 abandons the legacy monolithic System-on-Chip design for a disaggregated architecture, separating the CPU (BCM2712) and the I/O controller (RP1) across a PCIe interconnect. Operating in a #![no_std] environment without an underlying OS, we must build the entire abstraction stack from the ground up.

We will walk through the Embedded Rust Abstraction Stack layer by layer to solve specific hardware and concurrency problems:

• Layer 1 (Peripheral Access Crate): Defeating the LLVM optimizer. We examine why standard references to Memory-Mapped I/O (MMIO) invoke undefined behavior, how to use volatile intrinsics to prevent store merging, and how to safely map physical silicon registers using #[repr(C)] and operator overloading (Deref).
• Layer 2 (Hardware Abstraction Layer): Preventing physical hardware faults. We utilize Zero-Sized Types (ZSTs) and the Typestate pattern to encode hardware state machines into the type system, leveraging Rust’s move semantics to invalidate stale hardware states at compile time.
• Layer 3 (Traits & Dynamic Dispatch): Decoupling the OS from the hardware. We explore how dynamic dispatch (dyn) operates at the machine level using fat pointers and vtables to achieve hardware-agnostic design without a runtime.
• The Concurrency Paradox: Mutating global hardware state without standard library locks. We explore why Cell, RefCell, and Mutex either fail the borrow checker (!Sync) or cause single-core deadlocks in interrupt-driven systems. We resolve this by building a custom lock utilizing UnsafeCell and physical CPU interrupt masking to legally forge the Sync contract.

Takeaways

1. A clear mental model of the boundary between the Rust compiler (LLVM optimizations, pointer provenance) and physical hardware execution.
2. Practical techniques for using Zero-Sized Types and Typestates to enforce finite state machines at compile time, applicable to both hardware drivers and backend application logic.
3. A mechanical understanding of Rust’s interior mutability. Attendees will understand how UnsafeCell functions as the foundational primitive for bypassing the borrow checker, and the strict physical guarantees required to safely implement the Send and Sync traits.
4. Insight into bare-metal dynamic dispatch and how Rust achieves polymorphism via vtables without relying on an operating system.

Target Audience

Backend software engineers looking to understand the low-level mechanics of Rust’s concurrency and memory models, systems and firmware developers evaluating Rust for infrastructure, and developers interested in the exact execution physics of #![no_std] environments. No prior embedded experience is required.

Speaker Bio

Devansh Lodha is an undergraduate systems researcher at IIT Gandhinagar and an incoming Software Engineering Intern at Google. In the open-source ecosystem, he engineered the disaggregated boot sequence and PCIe/MSI-X interrupt pipeline for the Raspberry Pi 5 port of the official rust-embedded/rust-raspberrypi-OS-tutorials. He is currently working on the Hardware Abstraction Layer for the Raspberry Pi 5 in Flamingos, an experimental bare-metal Rust operating system.